Method and device for regenerating the integrity of the bit rate in a plesiosynchronous system
US4785464A · kind A · utility
6Cited by
7References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 7, 1987 |
| Grant date | Nov 15, 1988 |
| Priority date | — |
| Expiry date | Jan 7, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0608
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The network of the invention comprises, in the transmitter, a "marker" generator which inserts bits of a cyclical sequence into the binary data flow and, in the receiver, a marker processing circuit by which it is possible to identify the start of the marker cycle in order to re-justify the useful data signal in accordance with the detection of this start of a cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.