Bias scheme for achieving voltage independent capacitance
US4786828A · kind A · utility
11Cited by
18References
6Claims
0Family size
Inventor
Key dates
| Filing date | May 15, 1987 |
| Grant date | Nov 22, 1988 |
| Priority date | — |
| Expiry date | May 15, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/24
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
Described is a capacitive structure that can be fabricated with a digital MOS (Metal Oxide Semiconductor) process. The capacitive structure is comprised of two enhancement mode FET devices electrodes connected in series via their gate electrodes. The source and drain electrodes of each FET device are connected together. A third FET device, biased to operate within the linear or resistive region of its characteristic curve, is connected to the gate electrodes of the enhancement mode FET devices. The structure provides a voltage independent capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.