Electrically erasable fused programmable logic array
US4787047A · kind A · utility
7Cited by
11References
29Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 22, 1985 |
| Grant date | Nov 22, 1988 |
| Priority date | — |
| Expiry date | Mar 22, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17712
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic gate array employing a plurality of reprogrammable fuses having a logical NAND characteristic for logically connecting selected inputs to selected logic gates. The fuses are selectively programmed for providing appropriate signals to allow three modes of operation of the logic gate array; programming, erasure and normal logic operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.