Method of fabricating a thin film transistor
US4788157A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 28, 1987 |
| Grant date | Nov 29, 1988 |
| Priority date | — |
| Expiry date | Apr 28, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/15
Abstract
A method for fabricating a thin-film transistor having a stagger structure, in which the inner portion of the amorphous silicon layer doped as an ohmic contact layer to source and drain areas is defined by an insulating layer interposed therebetween, a step for forming source and drain electrodes on said amorphous silicon layer, which comprises a film forming process for forming a metal layer; a thermal treatment process for heating so as to generate a surface reaction between said metal layer and said amorphous silicon layer in order to selectively form a reaction layer only on said amorphous silicon layer; and a patterning process for selectively removing said metal layer so as to form source and drain electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.