Power-On-Reset (POR) circuit
US4788462A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 1987 |
| Grant date | Nov 29, 1988 |
| Priority date | — |
| Expiry date | Feb 12, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/22
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Power-On-Reset (POR) Circuit compares a logic supply voltage to a reference voltage and provides a logic voltage validity signal if the logic voltage is greater than the reference voltage; the circuit delays, on startup, the validity signal for a selected period and then provides a drive signal for driving a solid-state switch which provides an open circuit on the presence of the drive signal, indicating logic voltage validity, and a short circuit in its absence, indicating invalidity; and the circuit immediately disables the drive signal if the logic voltage falls below the reference voltage. The selected start-up delay period is independent of the supply voltage magnitude.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.