Logic analyzer
US4788492A · kind A · utility
21Cited by
3References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 26, 1987 |
| Grant date | Nov 29, 1988 |
| Priority date | — |
| Expiry date | Feb 26, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/25
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A logic analyzer has a plurality of data channels and clock channels which are connectible to a digital circuit. Each clock channel has associated therewith a temporary memory connected to all of the data channels, and the data stored in the temporary memories are successively delivered to a data memory under the control of master clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.