Priority logic system
US4788640A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 17, 1986 |
| Grant date | Nov 29, 1988 |
| Priority date | — |
| Expiry date | Jan 17, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved priority logic scheme for setting priority values determining priority of interrupts. Multi-level priority allows for varied priority values for single word and multiple-word block segment transfers. Registers allow for programmable priority values which can modify priority values during operation. Simplicity of the invention provides for priority circuitry which does not depend on clock cycles. Flexiblity of the circuitry allows for additional devices to be implemented within the scheme. The invention is described as developed in a single semiconductor chip with other processors to provide a single graphics chip capability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.