MOS I/O protection using switched body circuit design
US4789917A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 1987 |
| Grant date | Dec 6, 1988 |
| Priority date | — |
| Expiry date | Aug 31, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/213
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Switched body circuitry is provided to prevent a system I/O from being effected by the loss of power supply or ground to an MOS integrated circuit within the system. A semiconductor substrate of a first conductivity type has formed therein a well region of a second conductivity type opposite to that of the first conductivity type. First, second, third and fourth spaced-apart shallow diffusion regions of the first conductivity type are formed at the surface of the well region. A first gate electrode and the second and third diffusion regions combine to form an MOS transistor which is either an input pull up or pull down device or an output pull up or pull down driver of the MOS circuit. A second gate electrode and the third and fourth diffusion regions combine to define a first MOS switched body transistor. A third gate electrode and the first and second diffusion regions combine to define a second MOS switched body transistor. These two transistors control the potential of the I/O transistor's body (P-well or N-well) so as to keep the parasitic and ESD protection bipolar transistors and diode turned off during loss of power or ground to the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.