Digital phase-locked loop with random walk filter
US4791386A · kind A · utility
21Cited by
2References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 2, 1987 |
| Grant date | Dec 13, 1988 |
| Priority date | — |
| Expiry date | Jul 2, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1075
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital phase-locked loop in which the lead or lag of the phase of the input is compared to the phase of the output of the loop and the occurrences of the advance or retardation are filtered in a random walk filter in order to phase control the output. According to the invention, the time trend of the advance or retardation is determined. If there is a significant run of either advance or retardation, the random walk filter is adjusted so as to more quickly provide correcting output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.