Log encoder/decorder system
US4791403A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 1987 |
| Grant date | Dec 13, 1988 |
| Priority date | — |
| Expiry date | Jul 28, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/4006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high speed form of finite precision binary arithmetic coding comprises encoding/decoding performed in the logarithm domain, resulting in facilitated computation based on additions and subtractions rather than multiplications and divisions. In encoding and decoding, antilogs are used which are retrieved from an antilog table. The antilog table is characterized by the following constraints to assure decodability wherein for any two mantissas .alpha. and .beta. representing respective inputs to the antilog table: PA1 (a) antilog (.alpha.+.beta.).ltoreq.antilog (.alpha.) * antilog (.beta.); at least when (.alpha.+.beta.) is less than one; and PA1 (b) each antilog table output value is to be unique.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.