Apparatus and method for monitoring and controlling the prefetching of instructions by an information processing system
US4791557A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 1985 |
| Grant date | Dec 13, 1988 |
| Priority date | — |
| Expiry date | Jul 31, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information processing system includes a processor responsive to instructions for performing operations. The processor includes instruction queue for fetching and storing instructions in advance of execution and the system is responsive to certain of the instructions for causing execution of a corresponding sequence of instructions. A prefetch monitor includes circuitry for detecting instructions which may result in the execution of a corresponding sequence of instructions. The prefetch monitor further includes an instruction substitution circuit which is responsive to the detecting circuitry for inhibiting the reading of following instructions from a memory to the processor and is responsive to instruction fetching operation of the processor for reading null instructions to the processor. The prefetch monitor also includes a synchronization which is responsive to a fetching operation of the processor circuit for detecting transfer of execution to a next valid instruction, wherein the substitution circuit is responsive to the synchronization circuit for resuming reading of instructions from the memory to the processor with the next valid instruction. The synchronization includes…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.