Boolean logic layout generator
US4792909A · kind A · utility
51Cited by
8References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 7, 1986 |
| Grant date | Dec 20, 1988 |
| Priority date | — |
| Expiry date | Apr 7, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
To reduce the size of binary decision tree-type integrated circuit representations of boolean expressions, any boolean expression or sub-expression which is fully defined by one of its partial expressions is represented by only that one partial expression. If gate branching of the decision tree is a default case which is invoked only when both partial expressions are needed to define an expression or sub-expression. These reduced size expression trees readily map into CMOS cascade logic, thereby producing low power, reasonably compact, integrated circuit representations of boolean expressions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.