Package for semiconductor wafers
US4793488A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 7, 1987 |
| Grant date | Dec 27, 1988 |
| Priority date | — |
| Expiry date | Jul 7, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67383
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A sealable contamination proof container package bottom and top for storing and transporting a plurality of silicon wafers in a wafer carrier. The package bottom includes four sides, a continuous vertical surface for tape sealing surrounding the four sides, a lip positioned on a vertical edge, opposing hook latches on opposing sides, opposing hand grip recesses on the opposing sides and a raised bottom surface for package stacking. The package top includes four sides, a continuous vertical surface for tape sealing surrounding the four sides, a lip positioned on the vertical surface, opposing hook catches on the opposing side, a top surface with a raised stacking surface, a plurality of transparent inspection windows on the top surface, and two rows of wafer springs positioned on the underside of the top surface. The package top and bottom halves provide that a carrier mates between the package top and package bottom with the wafers in the carrier. The package top and bottom mate with the upper lip engaged against the lower lip, and the catches of the top engage with the latches of the bottom. In opening, the top package half is moved in a direction coinciding to the plane of the wa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.