Three phased pipelined signal processor
US4794517A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 1985 |
| Grant date | Dec 27, 1988 |
| Priority date | — |
| Expiry date | Apr 15, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This processor is a single chip implementation of an architecture that is designed to expeditiously handle certain tasks commonly associated with signal processing. Sequential multiply and accumulate operations, in particular, can be accomplished quite efficiently. The processor is pipelined in two areas. Instructions are passed through a three phase pipeline and consist of fetch, decode and execute, while the multiplier utilizes a two phase pipeline. The data flow is parallel and of 16-bit width throughout. The instruction store is maintained separately from the data store and provisions are included for having the processor enabled to read and write its own instruction store. Some parallel or compound instructions are implemented to permit transfer actions such as storage or I/O to or from instruction registers to occur concurrently with a compute action in different segments of the data flow. The arithmetic capabilities of the processor include both the separate multiplier and a full arithmetic logic unit. Two DMA modes are permitted. Extensive diagnostic capabilities, some of which utilize the processor's ability to read and write its own instruction store, are also included.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.