Pipelined single chip microprocessor having on-chip cache and on-chip memory management unit
US4794524A · kind A · utility
54Cited by
1References
10Claims
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Assignee
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Key dates
| Filing date | Jul 3, 1984 |
| Grant date | Dec 27, 1988 |
| Priority date | — |
| Expiry date | Jul 3, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A 32-bit central processing unit having a six-stage pipeline architecture with a cache memory and memory management unit all provided on a single integrated circuit (I.C.) chip but without any peripheral interface input/output circuits, clock or similar circuits on the chip in order to utilize the limited I.C. area for implementing the processor functions that most directly affect speed of operation and other performance factors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.