Dynamic read-write random access memory
US4794571A · kind A · utility
11Cited by
7References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 11, 1988 |
| Grant date | Dec 27, 1988 |
| Priority date | — |
| Expiry date | Jan 11, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic read-write random access memory (DRAM) including a memory cell, a word line and a bit line. The memory cell has a capacitor and a MOS transistor which has a gate connected to the word line, a drain terminal connected to the capacitor and a source terminal connected to the bit line. The DRAM further includes a supply circuit for applying to the bit line a voltage level having a value between the voltage level of the word line and the voltage level of the drain terminal of the MOS transistor when the memory cell is not selected, so as to prevent leakage current from flowing through the MOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.