Method of making a power IC structure with enhancement and/or CMOS logic
US4795716A · kind A · utility
49Cited by
8References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 19, 1987 |
| Grant date | Jan 3, 1989 |
| Priority date | — |
| Expiry date | Jun 19, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating a power IC structure which includes the following masking steps: PA1 1. CMOS P well mask PA1 2. JFET (short-channel implant) mask PA1 3. Field oxide growth mask PA1 4. Deep P+ mask PA1 5. Polysilicon mask PA1 6. DMOS P well mask PA1 7. n-/n+ mask PA1 8. Contact window mask PA1 9. Metalization mask PA1 10. Overglass mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.