Deflection current correction circuit
US4795949A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 8, 1988 |
| Grant date | Jan 3, 1989 |
| Priority date | — |
| Expiry date | Apr 8, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N3/223
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In a video display apparatus having an on-screen display feature (OSD), a vertical deflection circuit includes a vertical deflection winding coupled to a DC blocking capacitor. A deflection amplifier responsive to a sawtooth signal is coupled to the vertical deflection winding at an output terminal. A vertical sawtooth voltage generator that generates the sawtooth signal is coupled to an input terminal of the amplifier for driving the output stage at a vertical rate in a sawtooth manner to generate a sawtooth deflection current in the deflection winding. The sawtooth generator includes a capacitor that, during normal operation, is charged in a sawtooth manner via a resistor for developing a sawtooth signal. During a transition interval that follows a user initiated channel selection command, the frequency of the sawtooth signal becomes smaller. To prevent OSD character repositioning, a switch couples a first voltage via the resistor to the capacitor that causes the rate of change of the sawtooth signal and that of the deflection current to become smaller than during normal operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.