Linear predictive coding technique with one multiplication step per stage
US4796216A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 1987 |
| Grant date | Jan 3, 1989 |
| Priority date | — |
| Expiry date | Aug 13, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0225
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital filter for synthesized speech includes a full adder (72) that is multiplexed to perform multiplication and addition/subtraction operations. The inputs of the adder (72) are multiplexed by multiplexers (90) and (92). The adder (72) calculates Y-values and B-values. The B-values are input to a delay stack (116) and the Y-values are stored in a Y-register (78). One product is generated of a multiplier stored in a K-stack (128) and a multiplicand selected by a multiplexer (122). The multiplicand is a prestored summation that was earlier stored in a sum register (82). This product is stored in an ACC register (74) and utilized in both the calculation of the B-values and the Y-values. Therefore, only one multiplication is required for corresponding Y- and B-values, thereby reducing the number of multiplication steps required in processing each stage of a digital filter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.