Serial two's complement multiplier
US4796219A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 1, 1987 |
| Grant date | Jan 3, 1989 |
| Priority date | — |
| Expiry date | Jun 1, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pipelined multiplier which serially receives a signed input multiplicand and a signed multiplier to generate a signed serial output product is provided. The multiplier utilizes a technique which simplifies the addition of partial product bits by creating a uniform partial product array. Columns of partial product bits are sequentially added in a pipelined structure. Carry bits which are generated during the column addition of partial product bits are delayed in the pipeline and coupled back to the input of the pipeline at the appropriate time for another addition of column bits as product bits are serially outputted. By minimizing delays in the pipeline, multiplication of signed operands of large bit length may be quickly performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.