Arrangement for adjusting an impedance network in an integrated semiconductor circuit
US4797578A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 17, 1986 |
| Grant date | Jan 10, 1989 |
| Priority date | — |
| Expiry date | Dec 17, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H3/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated semiconductor circuit has the impedance networks (R11, R12, R13; R21, R22, R23) which can be adjusted with adjustment impedances (R14, R15; R24, R25). These are connected with the aid of adjustment circuits including a thyristor (TY1-TY4) and a short-circuiting zenerdiode (ZZ1-ZZ4). To avoid extra terminals for the adjustment circuit this is connected between two current terminals (6, 7) necessary for the normal operation of the semiconductor circuit. The electrode (11) of the thyristor (TY1-TY4) is connected to a signal input (E0-E3) which is also necessary for the normal operation. During adjustment, a voltage source is connected to one of the signal inputs (E0-E3) so that the corresponding thyristor (TY1-TY4) will become conductive and a current source is connected between the current terminals (6, 7). The current short-circuits the corresponding zenerdiode (ZZ1-ZZ4) so that the adjustment impedance is connected in parallel. The integrated circuit and its connection lines (12, 13, 14) are intended to withstand in normal operation the voltages and currents present during adjustment. The arrangement allows impedance adjustment of a ready-encapsulated integrated circu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.