Status register bit and delta
US4797652A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 17, 1987 |
| Grant date | Jan 10, 1989 |
| Priority date | — |
| Expiry date | Mar 17, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A unique circuit that unambiguously provides an output status bit and an output delta bit in response to an input data signal. This circuit does not require the use of a one shot. The circuit includes a first latch which latches the last status value, and an exclusive OR gate for comparing the previous input data value with the present input data value and provides an output data signal indicating whether change in the input data has occurred. If the exclusive OR gate indicates that a change in input data has occurred since the previous read, the new value of the input data is provided as an output status signal. Conversely, if the exclusive OR gate indicates that a change in the input signal has not occurred, the previous value of the input signal stored by the circuit is provided as an output status signal. Additional latches, which close at the onset of a read cycle, prevent either the delta bit or the status bit from changing during the read cycle. Another latch is set by the output status signal from the exclusive OR gate when the input data changes, and is only cleared by an actual read of delta bit which indicates that a change in input data has occurred, so a change in inpu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.