Reducing bipolar parasitic effects in IGFET devices
US4797724A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1982 |
| Grant date | Jan 10, 1989 |
| Priority date | — |
| Expiry date | Jun 30, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/854
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An IGFET is presented which includes a relatively low resistance path across the source-substrate junction to prevent parasitic bipolar effects while maintaining high component density in integrated circuits. The low resistance path across the source-substrate junction is formed by various methods including damaging the crystal structure at the junction interface, supplementing the damaged junction with a heavily doped region underlying the source region and spiking metallurgy. A particular application of the invention allows the prevention of latchup in CMOS devices. The invention also allows the source region of an IGFET to serve the dual functions of a source for a MOSFET as well as an ohmic contact to the underlying well or substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.