Logic redundancy circuit scheme
US4798976A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1987 |
| Grant date | Jan 17, 1989 |
| Priority date | — |
| Expiry date | Nov 13, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logic redundancy circuit scheme, comprising a plurality of pairs of logic circuit groups, each logic circuit group in a given pair having a respective logic node and a respective power control line, with each logic circuit group in a given pair generating substantially the same logic function signal on its respective logic node as the other logic circuit group in the given pair generates on its respective logic node. The circuit scheme further includes a plurality of isolation circuits having respective output nodes, with a different isolation circuit connected to each different logic circuit group logic node. These isolation circuits are powered at all times and each operates to provide an output signal on its output node indicative of the signal on the logic node connected thereto, while isolating the connected logic node from nets connected to the isolation circuit output node. The circuit scheme also includes means for electrically connecting together for bidirectional communication the logic nodes for each pair of logic circuit groups, prior to the connection to the isolation circuit associated therewith, and switching means connected to each of the power control lines assoc…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.