Semiconductor memory device having a CMOS sense amplifier
US4799197A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Sep 1, 1987 |
| Grant date | Jan 17, 1989 |
| Priority date | — |
| Expiry date | Sep 1, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device comprises a memory cell array comprising memory cells; a plurality of pairs of bit lines which are coupled to the memory cells and a data bus, each bit line being divided into at least two pairs of bit line parts; at least one sense amplifier provided between the pairs of bit line parts in each of the pairs of bit lines, for sensing a difference in potential between bit line parts in each pair, the sense amplifier being formed with complementary metal oxide semiconductor transistors; and at least a pair of transfer gates provided between a non-data bus side and a data bus side of the sense amplifier, the pair of transfer gates being held in an off-state when the sense amplifier is activated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.