Register-stack apparatus
US4800491A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 17, 1986 |
| Grant date | Jan 24, 1989 |
| Priority date | — |
| Expiry date | Nov 17, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4486
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A register-stack apparatus comprising first and second registers, first and second stack memories respectively coupled to store the register contents, first and second modifiers for providing the respective register contents in predetermined modified forms, and first and second select means for receiving a plurality of inputs including the modified register contents and, in accordance with a control command, applying a single output to the respective registers for storage therein, is disclosed. The register-stack apparatus is implemented in the controller of a computing system in which the controller receives macro-instructions from a host computer and, in response, provides microcode to an attached computing device. The register-stack apparatus is implemented as a program counter, I/O device, and plurality of register files and enables execution of CALLs, INTERRUPTs, and RETURNs with a minimal number of no-op instructions being issued to the attached computing device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.