Interleaved memory addressing system and method using a parity signal
US4800535A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 28, 1987 |
| Grant date | Jan 24, 1989 |
| Priority date | — |
| Expiry date | Apr 28, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high performance interleaved memory addressing system and method. A plurality of banks of random access memory devices are provided. The appropriate bank for a given memory address is selected based upon the parity among a preselected set of address bits including the least significant bit. A parity signal for selection of a memory bank is produced by a parity signal generation circuit, preferably a logic circuit. Typically, more than two memory banks would be employed, utilizing at least two parity signal generation circuits, each corresponding to respective least significant bits of the memory address. The output signals from the parity circuits are combined in a decoder to select the memory bank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.