Patent · US Expired

Integrable buffer circuit for voltage level conversion having clamping means

US4801824A · kind A · utility

6Cited by

6References

4Claims

0Family size

Assignee

Siemens Aktiengesellschaft · DE

Inventors

Christine Fellinger · Unterhaching, DE
Josef Einzinger · Spalt, DE
Ludwid Leipold · Munich, DE
Jenoe Tihanyi · Tauberbischofsheim, DE
Roland Weber · Munich, DE

Key dates

Filing date	Jul 21, 1987
Grant date	Jan 31, 1989
Priority date	—
Expiry date	Jul 21, 2007

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/018507
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A signal voltage (E) based upon a supply voltage must be converted to a signal voltage (A) with ground reference so as to enable further processing in a logic circuit. A simple level converter comprises a series connection of a MOSFET (T1) connected to the supply voltage; the MOSFET also comprises a resistor (T2). The source terminal of the MOSFET (T1) is located at the potential of the supply voltage. The voltage to be converted is applied between the gate terminal and the source terminal, and the converted voltage occurs at the resistor (T2). The two voltages are each limited by one Zener diode (D2, D1).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.