Bit line driver
US4802128A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 1986 |
| Grant date | Jan 31, 1989 |
| Priority date | — |
| Expiry date | Apr 10, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a bit line driver for MOS memory units of a microcomputer, which is connected between a pair of complementary bit lines and provided with an equalizing MOS transistor, a pair of active-load MOS transistors and a pair of clamping MOS transistors are connected separately to the complementary bit lines, and further the area of the clamping MOS transistors is determined to be about three times greater than that of the active-load transistors. An increase in the area of the clamping MOS transistors serves to decrease the internal resistance thereof, so that the clamping operation can be improved. A decrease in area of the active-load MOS transistor serves to increase the internal resistance, so that the access time can be improved. In addition, the driver can operate stably in response to a low power clock pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.