Error disbursing format for digital information and method for organizing same
US4802170A · kind A · utility
89Cited by
3References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 29, 1987 |
| Grant date | Jan 31, 1989 |
| Priority date | — |
| Expiry date | Apr 29, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2707
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Multiple stage interleaving through a memory matrix is utilized to separate adjacently disposed bits from bytes of digital information, in a reorganized bit stream. At least two stages of interleaving are required for the preferred embodiments of the invention which achieves a bit separation distance equal to the bit capacity of a plurality of either the matrix columns or rows, with that plurality being the number of adjacently disposed bits in each byte of digital information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.