Method and apparatus for interconnecting processors in a hyper-dimensional array
US4805091A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 1985 |
| Grant date | Feb 14, 1989 |
| Priority date | — |
| Expiry date | Jun 4, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A massively parallel processor comprising 65,534 (=2.sup.16) individual processors is organized so that there are 16 (=2.sup.4) individual processors on each of 4,096 (=2.sup.12) integrated circuits. The integrated circuits are interconnected in the form of a Boolean cube of 12 dimensions for routing of message packets. Each circuit board carries 32 (=2.sup.5) integrated circuits and each backplane carries 16 (=2.sup.4) circuit boards. There are eight (=2.sup.3) backplanes advantageously arranged in a cube that is 2.times.2.times.2. Each integrated circuit on a circuit board is connected to five integrated circuits on the same board which are its nearest neighbors in the first five dimensions. Further, each integrated circuit is also connected to four other integrated circuits on different circuit boards, but on the same backplane. Finally, each integrated circuit is also connected to three other integrated circuits, each on a different backplane. As a result of this arrangement, all message packets are first routed to nearest neighbor ICs located on the same circuit board; all message packets are then routed to nearest neighbor ICs located on the same backplane; and finally, all m…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.