Method of and arrangement for ordering of multiprocessor operations in a multiprocessor system with redundant resources
US4805106A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 9, 1987 |
| Grant date | Feb 14, 1989 |
| Priority date | — |
| Expiry date | Jul 9, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/825
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To lock use of shared information to itself in a multiprocessor system (100) having two independently and asynchronously operating processors (101, 111) whose main store units (102, 112) duplicate each other's contents, a processor must cause an atomic read-modify-write (RMW) operation to be executed on a semaphore in the duplicated main store units of both processors. To properly order execution of multiple such RMW operations, arbiters (106, 116) of system buses (105, 115) of the two processors communicate over an interarbiter channel (121). The arbiter of a source processor that wishes to perform an RMW operation notifies the other processor's arbiter over the interarbiter channel. Simultaneous attempts at notification by both arbiters are resolved in favor of one of them that is designated the master. The notifying arbiter prevents its processor from performing another RMW operation until the one RMW operation has completed thereon, but permits other operations to proceed normally. The notified arbiter prevents its processor from performing another RMW operation until the one RMW operation has been transferred via interprocessor links (107, 117) and bus (120) from the source pr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.