Selectable timing delay circuit
US4805195A · kind A · utility
59Cited by
4References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 10, 1986 |
| Grant date | Feb 14, 1989 |
| Priority date | — |
| Expiry date | Dec 10, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0037
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Disclosed is a programmable timing delay circuit for use in a synchronous system which includes a number of remote modules which must receive a synchronized clock in order to operate properly. The programmable timing delay circuit includes a plurality of delay paths which receive the reference clock signal and provide a variety of delays to a selector. The selector is controlled by an input means which allows selection of the optimum delay paths for a particular module. In this manner the clock signal received at each of the remote modules can be tuned to the desired synchronous phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.