Method and apparatus for recovering clock information from a received digital signal and for synchronizing that signal
US4805197A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 1986 |
| Grant date | Feb 14, 1989 |
| Priority date | — |
| Expiry date | Dec 18, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Inherent clock information included in a digital signal of the type in which binary information is represented by signal level transistions which are present on a periodic basis, such as a signal level transistion at a mid-location of a bit interval, is recovered by generating a pulse at each signal level transition, delaying that pulse by a half bit interval and by a full bit interval, respectively, and summing the generated, the half bit delayed and the full bit delayed pulses to recover the clock information. The recovered clock is used to write each binary level included in the received digital signal into a memory from which each stored binary level is read at a reference clock rate. Loss of synchronization between the received and read-out digital signals is detected by sensing a differential of predetermined magnitude in the write-in and read-out rates. Preferably, the detected differential in these rates is used to adjust the read clock rate in a direction which tends to null that differential, thereby restoring synchronism between the read out and written in digital signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.