ECL to CMOS translator
US4806799A · kind A · utility
19Cited by
5References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1988 |
| Grant date | Feb 21, 1989 |
| Priority date | — |
| Expiry date | Feb 26, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356017
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In integrated circuits which include both ECL and CMOS circuits, there is an ECL to CMOS translator which converts ECL logic levels to CMOS logic levels. To convert from ECL to CMOS levels, the ECL logic high is coupled to the base of an NPN transistor which provides a CMOS logic low. The ECL logic low is prevented from being coupled to the base of the NPN transistor. The CMOS logic high is obtained by an analogous second circuit which is responsive to a complementary ECL signal the output of which is coupled to a P channel transistor. The P channel transistor either provides the CMOS logic high output or is non-conductive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.