Phase comparator lock detect circuit and a synthesizer using same
US4806878A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 17, 1987 |
| Grant date | Feb 21, 1989 |
| Priority date | — |
| Expiry date | Jul 17, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A lock detect circuit (FIG. 3) for use in a synthesiser of the type comprising a phase comparator (5), a reference frequency source (11, 13, 15) a variable frequency oscillator (1), a variable divider (3) and a loop amplifier (7). The circuit includes logic gates (31, 33, . . . 41) to monitor the frequency `up` and frequency `down` error signals (C.sub.U, C.sub.D) produced by the comparator (5) and provides an `in-lock` indication (S) when frequency `up` or frequency `down` signals exclusively are detected in a predetermined period ( .sub.D). Accordingly this circuit may comprise a variable delay (31) an inverter (33) an AND-gate (35) and an OR-gate (39) for generating a comparison signal: EQU f'.sub.E =F.sub.N .multidot.C.sub.D +C.sub.U where f.sub.N is the signal from the inverter time delay pair derived from the divider output. This signal is fed to a series of flip-flops (37) clocked by the frequency down signal. The outputs (Q) of the flip-flops (37) are referred to a second AND-gate (41) to generate the `in-lock` signal (S). To accommodate under critical damping a latch (43) may be provided at the signal output. Alternatively two such circuits, one with reversed input connect…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.