Static memory cell using a heterostructure complementary transistor switch
US4807008A · kind A · utility
7Cited by
2References
7Claims
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Assignee
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Key dates
| Filing date | Sep 14, 1987 |
| Grant date | Feb 21, 1989 |
| Priority date | — |
| Expiry date | Sep 14, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/05
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A heterostructure complementary transistor switch (HCTS) is fabricated using epitaxial layers on a substrate to form the desired P-N-P-N (or N-P-N-P) complementary structure in III-V compound semiconductor materials. Two HCTS are formed on a single substrate to form a memory cell. A collector and a base on one of the HCTs are connected to a base and a collector, respectively, on the other HCTS to form the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.