Instruction issuing mechanism for processors with multiple functional units
US4807115A · kind A · utility
361Cited by
10References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 14, 1987 |
| Grant date | Feb 21, 1989 |
| Priority date | — |
| Expiry date | Oct 14, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8053
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction issuing mechanism for boosting throughput of processors with multiple functional units. A Dispatch Stack (DS) and a Precedence Count Memory (PCM) are employed which allow multiple instructions to be issued per machine cycle. Additionally, instructions do no have to be issued according to their order in the instruction stream, so that non-sequential instruction issuance occurs. In this system, multiple instruction issuance and non-sequential instruction issuance policies enhance the throughput of processors with multiple functional units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.