Interprocessor communication
US4807116A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 1987 |
| Grant date | Feb 21, 1989 |
| Priority date | — |
| Expiry date | May 18, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/173
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a multiprocessor system comprising a plurality of individual processor modules interconnected by a bus structure, including a bus controller, for providing communication between the processor modules, a method and apparatus for interprocessor communication includes one of the processor modules sending a request signal to the bus controller to request a transmission; the bus controller polling the processor modules to identify the requesting processor module; the requestor processor module responding to the poll with the identification of the receiver processor module; the bus controller interrogating the receiver processor module to determine its status (i.e., busy or available); and the bus controller then signaling transmission commencement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.