Postage meter with microprocessor controlled reset inhibiting means
US4807141A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 16, 1985 |
| Grant date | Feb 21, 1989 |
| Priority date | — |
| Expiry date | Dec 16, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a postage meter which includes a computer, a power supply for energizing the computer, a non-volatile memory for storing postage meter operating data, and wherein the computer includes a microprocessor adapted for processing the operating data, there is provided an improvement for protecting the operating data. The improvement comprises: the computer including (a) apparatus for detecting respective high level and low level output voltage signals from the power supply; (b) a first switching circuit operable in response to the detection of a high level output voltage signal for providing a power-up signal to the microprocessor and operable in response to the detection of a low level output voltage signal for providing a power-down signal to the microprocessor; (c) a second switching circuit operable in response to the detection of said high level signal for providing a not-reset signal to said microprocessor and operable in response to the detection of said low level signal for providing a reset signal to said microprocessor; and (d) apparatus for enabling operation of the non-volatile memory after the microprocessor has been provided with the power-up and not-reset signals, where…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.