Tristate output circuit with selectable output impedance
US4808853A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 25, 1987 |
| Grant date | Feb 28, 1989 |
| Priority date | — |
| Expiry date | Nov 25, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09429
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A tristate output circuit includes a pair of transistors having sources connected to a switchable current source and drains separately coupled to a voltage source through separate resistors and switching transistors. When the current source and switching transistors are on, the circuit operates in a back termination mode wherein it amplifies a differential input signal applied across the gates of the transistor pair to produce a differential output signal across their drains for transmission on a transmission line. The load resistors are sized to match the characteristic impedance of a transmission line so as to properly terminate the transmission line. In an open drain mode, the switching transistors are off, uncoupling the drains of the transistor pair from the voltage source so as to increase output impedance. In a tristate mode, the current source and switching transistors are turned off, thereby turning off the transistor pair and rendering the output impedance of the circuit substantially infinite.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.