Dual limit programmable linear signal limiter
US4808858A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 25, 1988 |
| Grant date | Feb 28, 1989 |
| Priority date | — |
| Expiry date | Jan 25, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A current signal limiter provides precise minimum and maximum current limiting. Both maximum and minimum current limits are easily programmable. The signal limiter operates at maximum frequency response without inversion of the input signal. Current signal limiting is achieved by an NPN transistor biased in a common base configuration with the base coupled to a reference voltage source and the collector providing the output current, a series diode coupled to the emitter of the transistor for receiving a trickle current which prevents the transistor from turning off as well as setting a minimum current limit, and a diode matrix for receiving two reference currents and an input current. The diode matrix steers the input and reference currents to the transistor or to the reference voltage source, depending on the magnitude of the input and reference currents. The minimum and maximum current limits are programmable by adjusting the values of the reference currents and the trickle current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.