Phase-locked loop for a modem
US4808937A · kind A · utility
11Cited by
7References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 15, 1986 |
| Grant date | Feb 28, 1989 |
| Priority date | — |
| Expiry date | Jul 15, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A modem and an improved phase-locked loop used in the modem. A presettable counter (251) generates the desired signal (TXCLKOUT). The reference input clock signal (TXCLKIN) and the generated clock signal (TXCLKOUT) are compared by an exclusive-OR gate (254). The output of the gate (254) is sampled by two flip-flops (256,266) before and after a rising edge of the TXCLKOUT signal. If the TXCLKIN and TXCLKOUT signals differ by more than a desired phase window a logic circuit (264) adjusts the preset inputs of the counter (251) so that the TXCLKIN and TXCLKOUT signals are in phase within the desired phase window.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.