Very high speed line adapter for a communication controller
US4809155A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 1987 |
| Grant date | Feb 28, 1989 |
| Priority date | — |
| Expiry date | Apr 2, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/124
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The high speed line adapter comprises a bit handling layer (34,46) and a byte handling layer (36,50) and a receive queue mechanism (48). The bit layer receives the frames from the high speed line 9. It performs the SDLC protocol, it removes the flag and BCC characters and adds one ending condition control character which indicates whether the frame was correctly received or not. It causes the address and control fields, the data if any and the ending condition character to be stored into a receive queue buffer at the first free address. The byte layer 50 takes out the frame characters from the receive queue as soon as a pool buffer is available in the memory of the central unit of the communication controller. It sends the data if any to said memory through a direct access memory bus and sends the address and control fields and the ending condition to the microprocessor of the adapter. The provision of the receive queue mechanism allows high speed lines to be connected to a communication controller, without modifying its network control program.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.