Saving registers in data processing apparatus
US4809162A · kind A · utility
6Cited by
4References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 4, 1987 |
| Grant date | Feb 28, 1989 |
| Priority date | — |
| Expiry date | Jun 4, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3868
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data processing apparatus includes a data path having a path delay, from a source latch point to a destination latch point, of greater than one clock cycle. For an n-cycle path, where the path delay is between n- 1 and n clock cycles, data is latched into the source latch point at least n clock cycles in advance of the cycle on which it is needed at the destination latch point. The data and gating signals along the data path are held glitch-free in the source latch point until after the clock cycle on which the data is used in the destination latch point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.