Concurrent processing of data operands
US4809171A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 1988 |
| Grant date | Feb 28, 1989 |
| Priority date | — |
| Expiry date | Jan 21, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operand processing unit (10) carries out processing of operands in a computer. The unit (10) includes a plurality of operation circuits (12, 14, 16, 18, 20). A source bus (22) provides one operand per clock cycle to the operation circuits (12, 14, 16, 18, 20). A destination bus (24) receives one resultant per clock cycle from the operation circuits (12, 14, 16, 18, 20). Within each operation circuit there is provided an operand processing circuit (80) which performs a selected function with the received operands. These functions include, for example, multiplication, division, addition, subtraction, logical AND, and shift. Logical circuitry provides a priority assignment to the operation circuits (12, 14, 16, 18, 20) for sequencing the loading of operands into the highest priority operation circuit (12, 14, 16, 18, 20) which is not busy processing operands within its corresponding operand processing circuit (80). The operand processing unit (10) provides concurrent processing of operands to enhance processing speed. The operands and resultants are handled in a manner such that there is a uniform and sequential flow of operands from a source, such as main memory, and a uniform and…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.