Sample-and-hold phase detector circuit
US4810904A · kind A · utility
109Cited by
12References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 6, 1988 |
| Grant date | Mar 7, 1989 |
| Priority date | — |
| Expiry date | Jun 6, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/199
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A sample-and-hold phase detector (30, 80, 90, 100, 110) which includes sample-and-hold circuitry (FIG. 6) having variable efficiency. Specifically, the sample-and-hold circuitry provides a sampling pulse of variable width which is controlled to be wider during acquisition and narrower during steady-state operation. Also provided is protection circuitry to neutralize leakage of the input signal to the output of the circuit when a sample control signal is not present.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.