Vertical inverter circuit
US4810906A · kind A · utility
19Cited by
6References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 22, 1988 |
| Grant date | Mar 7, 1989 |
| Priority date | — |
| Expiry date | Apr 22, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
Abstract
One embodiment of the present invention includes a vertical inverter. A layer of P-type material is formed on the surface of an N+-type substrate, followed by formation of an N+ layer, a P+ layer, an N- layer, and a P+ layer. (Of course different doping configurations may be used and remain within the scope of the invention.) A trench is then etched along one side of the stack thus formed and a connector is formed to the middle P+ and N- layers. Another trench is then formed where a gate insulator and a- gate are formed. The gate serves as the gate for both the N-channel and P-channel transistors thus formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.