FET switch circuit having small insertion loss and exhibiting stable operation
US4810911A · kind A · utility
Inventor
Key dates
| Filing date | Nov 16, 1987 |
| Grant date | Mar 7, 1989 |
| Priority date | — |
| Expiry date | Nov 16, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/693
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a switch circuit comprising one common input/output terminal, two switching input/output terminals, series field effect transistors respectively inserted between the common input/output terminal and the two switching input/output terminals, shunt field effect transistors respectively inserted between the two switching input/output terminals and the ground, and resistors respectively inserted between the ground and the common input/output terminal and between the ground and the two switching input/output terminals, the resistors having the resistance values smaller than that of the shunt field effect transistors at OFF state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.