Clamping circuit for an analog to digital converter
US4811016A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 1986 |
| Grant date | Mar 7, 1989 |
| Priority date | — |
| Expiry date | Oct 21, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/164
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A clamping circuit clamps a threshold of an analog to digital converter (ADC) to a signal level just below the black level of a television signal. PA1 During the blanking period, a negative-going peak is superimposed on the input signal to produce the waveform. Each time this crosses the 0000,0001 threshold of the ADC, the polarity of the output of a comparator changes. The comparator compares the ADC output and a reference value. The input signal is biased according to the integral of the comparator output. When signal levels are stable, the comparator output is symmetrical, its integral is zero and no change occurs in the biasing. If signal levels drift, the negative going peak crosses the threshold for a second time relatively sooner or later. The comparator output becomes assymmetric and has a non-zero integral. Consequently, the biasing level changes to compensate for the drift.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.